Date:
Feb 25, 2014
Location
San Jose, California, US
Req ID: 14459
Nearest Major Market: San Jose
Nearest Secondary Market: Palo Alto
Job Segment: Electrical, Engineer, Network, Design Engineer, Telecom, Engineering, Technology
ASIC Engineer – Network Processor Team
Job Level: ASIC Engineer
Job Location: San Jose, CA, USA
Next Generation IP Solutions - IP Networking Team
By 2020, there will be 50 billion connections to the internet, whereby anything that can benefit from an internet connection will be connected. We are already starting to see this today. But, it’s just the beginning. Over the last 3-4 years Ericsson has invested billions of dollars to move from a #1 position in Wireless Infrastructure (where we have >50% market share) to take claim as the #1 in Converged Infrastructure…end-to-end. There are a whole host of challenges you face when creating a single, fully converged, infrastructure that handles everything. This is a rare opportunity to be a part of something big…that’s technically challenging, and innovative, as well as change the world by creating a networked society!
For the last 15 years we’ve built ASICs, in-house, for these products our multi-service edge routing products. We are working on brand new chip architecture for our future generation platform (the Smart Services Router ). The ASICs we are building are state-of-the-art multi-core network processors that will be far more complex than previous generation ASICs. The will have more computational power, higher interface throughput, Parallel execution threads, higher clock frequency, Brand new architecture
Job Overview:
Candidate Profile:
We are proud to be an EEO/AA employer M/F/D/V. We maintain a drug-free workplace and perform pre-employment substance abuse testing
Primary country and city: United States (US) || California || San Jose || Stud&YP
Job Level: ASIC Engineer
Job Location: San Jose, CA, USA
Next Generation IP Solutions - IP Networking Team
By 2020, there will be 50 billion connections to the internet, whereby anything that can benefit from an internet connection will be connected. We are already starting to see this today. But, it’s just the beginning. Over the last 3-4 years Ericsson has invested billions of dollars to move from a #1 position in Wireless Infrastructure (where we have >50% market share) to take claim as the #1 in Converged Infrastructure…end-to-end. There are a whole host of challenges you face when creating a single, fully converged, infrastructure that handles everything. This is a rare opportunity to be a part of something big…that’s technically challenging, and innovative, as well as change the world by creating a networked society!
For the last 15 years we’ve built ASICs, in-house, for these products our multi-service edge routing products. We are working on brand new chip architecture for our future generation platform (the Smart Services Router ). The ASICs we are building are state-of-the-art multi-core network processors that will be far more complex than previous generation ASICs. The will have more computational power, higher interface throughput, Parallel execution threads, higher clock frequency, Brand new architecture
Job Overview:
- ASIC engineer responsible for designing/verifying in any of the following key areas of our next generation processor:
- Traffic Manager
- Memory sub-system including cache
- Packet Classification (Layer 2 classification experience is big plus)
- Algorithmic Search Units
- Execution Units
- Work with Design & DV Leads to provide solutions for complex technical challenges
- Responsible for validating RTL from the uArch definition or develop RTL from uArch definition
- Responsible for developing C/C++/System Verilog blocks for verification
- Responsible for the coverage closure of the block(s)
- Will work closely with SDK, system and software teams
Candidate Profile:
- BS/MS degree in Computer/Electrical Engineering or equivalent
- Course work and projects in areas of Processor Architecture/Processor Pipeline design/ Cache design/performance analysis is definite plus
- Very strong programming skills in C/C++/Verilog
- Working knowledge of network protocols and standards
- Outstanding academic track record
- Strong analytical and problem-solving skills
- Strong driver with a keen sense of ownership and result orientation
We are proud to be an EEO/AA employer M/F/D/V. We maintain a drug-free workplace and perform pre-employment substance abuse testing
Primary country and city: United States (US) || California || San Jose || Stud&YP
Nearest Major Market: San Jose
Nearest Secondary Market: Palo Alto
Job Segment: Electrical, Engineer, Network, Design Engineer, Telecom, Engineering, Technology
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