Job details
Date:
Feb 5, 2014
Location
, California, US
Req ID: 374
Job Segment: Engineer, Network, Design Engineer, Hardware Engineer, R&D Engineer, Engineering, Technology
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Principal Hardware Engineer – High Speed Board Design *LI-GP1
San Jose, CA, USA
Project area: the Smart Services Router & Next Generation Solutions
By 2020, there will be 50 billion connections to the internet, whereby anything that can benefit from an internet connection will be connected (i.e. Networked Society). Over the last 3+ years Ericsson has invested billions of dollars to move from the #1 position in Wireless Infrastructure to take claim as the #1 in end-to-end Converged Infrastructure. There are not many players that have end-to-end capability. There are a whole host of challenges you face when creating a single, fully converged, infrastructure that handles everything.
Job Overview (includes but not limited to):
Qualifications
Primary country and city: United States (US) || California || No Selection || R&D
San Jose, CA, USA
Project area: the Smart Services Router & Next Generation Solutions
By 2020, there will be 50 billion connections to the internet, whereby anything that can benefit from an internet connection will be connected (i.e. Networked Society). Over the last 3+ years Ericsson has invested billions of dollars to move from the #1 position in Wireless Infrastructure to take claim as the #1 in end-to-end Converged Infrastructure. There are not many players that have end-to-end capability. There are a whole host of challenges you face when creating a single, fully converged, infrastructure that handles everything.
Job Overview (includes but not limited to):
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Guide and influence the product definition at the chip, board, and system level based on performance, power, and cost tradeoffs
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Support the ASIC and Hardware development groups during the entire product development cycle
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Design the signaling channels for serial/parallel high speed interfaces and the power distribution network (PDN) for processors, memories, optics, etc.
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Model and simulate traces, vias, connectors and other complex interconnect structures
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Analyze timing, signal quality, crosstalk, jitter, eye diagrams, bit error rate, impedance, SSN and EMI in high speed interfaces
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Analyze hot spot, voltage drop, decoupling, transient noise and EMI in power distribution networks
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Create signal integrity and power integrity guidelines and routing rules; synergize with physical design team (both in house and outside) for their implementation
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Validate the design through measurement and correlation
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Help devise process and methodology improvements through automation and software to augment the Signal Integrity team scalability and effectiveness
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Establish and execute HW development project plans, collaborate with colleagues across Product Development Unit IP to achieve strategic objectives
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Provide Career Management support to his/her HW Team through coaching, technical mentoring and training as well as by applying a culture of performance based rewards
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Forecasting and managing people and capital requirements
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Drive actions to closure, and be able to establish and drive cross-organizational initiatives
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Travel to and interact with other Ericsson locations.
Qualifications
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10+ years of industry experience in the design and simulation of high-speed signals
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Excellent Interpersonal Skills, Leadership Skills, Ability to undertake loosely defined goals, Create order, and Drive closure
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Ability to organize, delegate, and effectively deliver to large and complex programs
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Conflict resolution skills including ability to bridge style difference, gaps in language skills, and differences in incentives
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Excellent interpersonal, verbal, listening, and written communicationSelf-motivated problem solver
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Bachelor degree in Engineering required
Primary country and city: United States (US) || California || No Selection || R&D
Job Segment: Engineer, Network, Design Engineer, Hardware Engineer, R&D Engineer, Engineering, Technology
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