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| Job description | ||||||||||||||||||||||||||||||||||||
| As a design-implementation intern / Co-op, you will be
responsible for the physical layout and performance of chip designs
within IBM's microelectronics technologies. Integration engineers use synthesized logic to floorplan chips within a certain area, given many constraints, including: logical function, placement restrictions, timing results, clock design, noise considerations, and package footprint. The physical layout of chips involves considerable challenges in the form of wiring congestion, multiple wire sizes and layers, and technology ground rules. Timing engineers analyze physical designs for performance and compliance to the design specification. They will have an understanding of the process corners in various silicon technologies, extract physical structures for noise analysis, and work closely with the integrators to resolve timing issues and "close timing" for a particular core frequency for the chip tapeout. | ||||||||||||||||||||||||||||||||||||
Required
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| IBM is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age, or veteran status. IBM is also committed to compliance with all fair employment practices regarding citizenship and immigration status. |
Thursday, 14 November 2013
Chip/Unit Integration Engineering Professional
Posted by Unknown on 23:00 with No comments
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