- Job Number: 18071657
- Santa Clara Valley, California, United States
- Posted: Nov. 6, 2013
- Weekly Hours: 40.00
Job Summary
In
this highly visible role as a senior level member of a small timing
team, you will be an integral part of the effort to maximize the
performance of Apple silicon.
You will utilize your hands on experience in timing analysis, cell
characterization, and power analysis to develop/define timing
methodologies, analysis flows and optimization strategies.
These flows will be utilized by design engineers to develop advanced
chips and technologies for Apple mobile products.
Key Qualifications
- Typically requires 8+ years of CAD or Design experience in timing. or related analysis.
- You should have experience with timing, power and signal integrity analysis tools.
- Solid understanding the strengths and weaknesses of timing tools and impact of timing signoff methodology on design closure.
- Experience with transistor-level analysis, library cell characterization, power, or signal integrity analysis.
- Good CAD scripting skills in any of the following: Perl or TCL or SKILL or Python or C.
Description
In this highly visible role, responsibilities include:
*Defining, implementing and reviewing signoff timing analysis methodologies.
*Utilizing state-of-the-art tools such as Spice, Nanotime and Primetime.
*Working closely with the CAD team to develop robust timing, power and signal integrity analysis infrastructure.
* Cross functionally work with our design engineers to drive design closure to performance and power targets.
Education
•MS/BS Degree in technical discipline
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